Udemy - Learn FPGA design with VHDL - Sobel Filter Edge Detection

Learn FPGA design with VHDL : Sobel Filter Edge Detection

https://WebToolTip.com

Published 9/2025
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Language: English | Duration: 3h 58m | Size: 1.68 GB

Understand and build an edge detector based on Sobel filter from scratch in VHDL

What you'll learn
Fundamentals of image processing and edge detection
Fundamentals of digital arithmetic and signed and unsigned manipulation with VHDL
Finite state machines
Best practices for modular, reusable, VHDL design
Architecting a hardware design and implementing in VHDL
Hands-on practical lab
Project automation with Makefile and python scripts

Requirements
Basic notions on digital electronics and VHDL are needed to get the most from this course